1. Field of the Invention
The present invention relates to a method of forming wiring on a plurality of semiconductor devices from a single metal plate, and a semiconductor construction assembly formed by the method.
2. Description of the Related Art
A conventional semiconductor device is known in which a semiconductor construction is embedded on one surface of a semiconductor substrate, and columnar external connection electrodes are arrayed on the semiconductor construction in matrix form. Generally, a planar area of the semiconductor substrate is small, and thus the number of external connection electrodes that can be arrayed within the area is limited.
For this reason, an insulating film is formed on the periphery of the side surfaces of the semiconductor construction, an upper-layer insulating film is provided on top of the insulating film and the semiconductor construction, and an upper-layer wiring having an external connection pad section is formed on top of the upper-layer insulating film. In this instance, the upper-layer wiring is connected to the external connection electrodes of the semiconductor construction via a contact hole formed in the upper-layer insulating film. When a configuration such as this is applied, an integrated circuit of a larger scale having a large number of external connection electrodes can be miniaturized because the upper-layer insulating film has a greater planar area than the semiconductor construction.
A method described in Japanese Patent Application Laid-Open (Kokai) Publication No. 2007-134738 is known as a manufacturing method of a semiconductor such as described above. In this prior patent document, as shown in FIG. 11 to FIG. 13, a method is described in which a contact hole is formed in the upper-layer insulating film by laser beam irradiation, and after a base metal layer is formed on the overall surface of the upper-layer insulating film including the top surfaces of the columnar external connection electrodes exposed via the contact hole, an upper-layer metal layer is formed by electroplating, and then patterning is performed by a photolithography method to form the upper-layer wiring.
As another method, a method described in Japanese Patent Application Laid-Open (Kokai) Publication No. 2004-349361 is known. In the method described in this prior patent document, manufacturability is further improved. As shown in FIG. 13 to FIG. 15, conical projection electrodes are formed in advance on a metal plate in positions corresponding to connection electrodes, and after the metal plate is heat pressed from above an upper-layer insulating film, and each projection electrode is wedged into the upper-layer insulating film, the tips of the projection electrodes are placed in contact with the surfaces of corresponding columnar external connection electrodes, and then patterning is performed on the metal plate by the photolithography method to form the upper-layer wiring.
However, in the method described in Japanese Patent Application Laid-Open (Kokai) Publication No. 2007-134738, a small-area contact hole is formed on the upper-layer insulating film, and then the upper-layer wiring is formed by electroplating. Therefore, a void (air bubble) is formed within the contact hole, and because of this, a disconnected area is formed or uniform plating thickness is difficult to ensure. That is, there is a problem that highly reliable connection is not ensured with regard to a fine pitch.
Moreover, in the method described in Japanese Patent Application Laid-Open (Kokai) Publication No. 2004-349361, when a large number of semiconductor constructions are arrayed on a base, and the metal plate on which the projection electrodes are formed is heat pressed, each semiconductor construction is displaced differently from each other. That is, there is a problem that, with a single metal plate, alignment between all external connection electrodes on the semiconductor constructions and projection electrodes on the metal plate is difficult, and the yield cannot be improved.